MARC

 008021018s2001        us                        000      eng
■020    ▼a0-471-41209-0
■0801  ▼a681.3.06
■082    ▼a600▼223
■090    ▼a600▼bM621a
■1000  ▼aOberman,  Michael  J.Flynn,  Stuart  F.
■24510▼aAdvanced  Computer  Arithmetic  Design▼dMichael  J.Flynn,  Stuart  F.  Oberman  저.
■260    ▼a미국▼bJohn  Wiley  &  Sons,  Inc▼c2001
■300    ▼a325p.▼c25cm
■505    ▼a1.  Integer  Addition▼c1▼a1.1  Background▼c1▼a1.2  Ling  Adders▼c6▼a1.3  Adder  Implementations▼c7▼a1.4  An  ECL  Ling  Adder▼c10▼a1.5  A  CMOS  Ling  Adder▼c14▼a1.6  Conclusion▼c21▼a2.  Floating-Point  Addition▼c23▼a2.1  Improved  Alogrithms  for  High-Speed  FP  Addition▼c23▼a2.2  Variable-Latency  FP  Addition▼c3300▼a2.3  Performance  Results▼c3811▼a2.4  Conclusion▼c4222▼a3.  Multiplication  with  Partially  Redundant  Multiples▼c4333▼a3.1  Introduction▼c4344▼a3.2  Background▼c4355▼a3.3  Redundant  Booth▼c5066▼a3.4  Booth  3  with  Fully  Reundant  Partial  Products▼c5077▼a3.5  Booth  3  with  Partially  Redundant  Partial  Products▼c5288▼a3.6  Booth  with  Bias▼c5399▼a3.7  Vonclusion▼c6300▼a4.  Multiplier  Topologies▼c6511▼a4.1  Review  of  Issues  in  Partial-Product  Summation▼c6622▼a4.2  Regular  Topologies▼c6833▼a4.3  Irregular  Topologies▼c8944▼a4.4  Conclusion▼c9955▼a5.  Technology  Scaling  Effects  on  Multipliers▼c10166▼a5.1  Effects  of  Smaller  Feature  Sizes▼c10177▼a5.2  Wire  Effects▼c10288▼a5.3  Binary  Trees  vs  Procedural  Layouts▼c10699▼a5.4  Scaling  Effects  on  Encoding  Schemes▼c10900▼a5.5  Power▼c11411▼a5.6  Conclusion▼c11622▼a6.  Design  Issues  in  Division▼c11733▼a6.1  Introduction▼c11744▼a6.2  System  Level  Study▼c11855▼a6.3  Results▼c12066▼a6.4  Conclusion▼c13077▼a7.  Minimzing  the  Complexity  of  SRT  Tables▼c13388▼a7.1  Teory  of  SRT  Division▼c13499▼a7.2  Implementing  SRT  Tables▼c13800▼a7.3  Experimental  Methodology▼c14311▼a7.4  Results▼c14522▼a7.5  Conclusion▼c15033▼a8.  Very  high-Radix  Division▼c15344▼a8.1  Taylor  Series  Expansion▼c15355▼a8.2  algorithm  A▼c15466▼a8.3  Algorithm  B▼c16277▼a8.4  Algorithm  C▼c17188▼a8.5  Related  Algorithms▼c17999▼a8.6  Conclusion▼c18200▼a9.  Using  a  Multiplier  for  Function  Approximation▼c18311▼a9.1  Proposed  Method:  Implementation▼c18322▼a9.2  Proposed  Method:  Derivation▼c19233▼a9.3  Reciprocal,  Division,  and  Square  Root▼c20744▼a9.4  Conclusion▼c23055▼a10.  FUPA▼c23566▼a10.1  Introduction▼c23577▼a10.2  Background▼c23788▼a10.3  Components  of  FUPA▼c23799▼a10.4  Microprocessor  FPI  Comparisons▼c24400▼a10.5  Limitations  of  FUPA▼c24911▼a10.6  ConClusion▼c24922▼a11.  High=Speed  Clocking  Using  Wave  Pipelining▼c25133▼a11.1  Background▼c25144▼a11.2  Theory▼c25455▼a11.3  Device  Technologies:  Applicability  and  Performance▼c25966▼a11.4  Performance  Limits  of  Wave  Pipelining▼c26077▼a11.5  Desing  Optimizations▼c26588▼a11.6  SNZP  Wave-Pipeline  Demonstration  VLSI▼c27399▼a11.7  Conclusion▼c28300▼a12.  Rational  Arithmetic▼c28511▼a12.1  Introduction▼c28522▼a12.2  Continued  Fractions▼c28733▼a12.3  The  M-log-Fraction  Transformation▼c29044▼a12.4  The  Signed-Digit  M-log  Fraction▼c29255▼a12.5  A  Rational-Arithmetic  Unit▼c29366▼a12.6  A  Shift-and-Add-Based  Rational-Arithmetic  Unit▼c29877▼a12.7  VLSI  Implementation  Of  Rational-Arithmetic  Units▼c30188▼a12.8  Higher-Rational  Artithmetic▼c30299▼a12.9  Related  Work▼c30400▼a12.10  Conclusions▼c30611▼a12.11  Historical  Notes  on  Continued  Fractions  in  Arithmetic▼c30622▼aBibliography▼c30933▼aIndex▼c32144
■9500  ▼b￦116550

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