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(Verilog-HDL과 Xilinx Vivado(18.1) 및 FSKⅢ를 활용한)FPGA 설계기초
(Verilog-HDL과 Xilinx Vivado(18.1) 및 FSKⅢ를 활용한)FPGA 설계기초
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MARC
008180828s2018 ulka 000a kor■020 ▼a9791159064180
■082 ▼a621.395▼223
■090 ▼a621.395▼b이74ㅇ
■1001 ▼a이제현
■24520▼a(Verilog-HDL과 Xilinx Vivado(18.1) 및 FSKⅢ를 활용한)FPGA 설계기초▼d이제현 지음
■260 ▼a서울▼b복두출판사▼c2018
■300 ▼a184 p.▼b삽화▼c26 cm.
■9500 ▼b\12000
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