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Multiple-Cel回UpsetTolerant 6T SRAM Using NMOS-Centered Cell Layout
Multiple-Cel回UpsetTolerant 6T SRAM Using NMOS-Centered Cell Layout
Detailed Information
- 자료유형
- 기사
- ISSN
- 09168508
- 서명/저자
- Multiple-Cel回UpsetTolerant 6T SRAM Using NMOS-Centered Cell Layout / ・ S husuke YOSHIMOTO,S hunsukeO KUMURA, KojiN II,H iroshi KAWAGUCHI,and MAsahiko YOSHIMOTO
- 형태사항
- pp. 1579
- 모체레코드
- 모체정보확인
- Control Number
- gtec:383857
MARC
008171215s2013 aa eng■022 ▼a09168508
■245 ▼aMultiple-Cel回UpsetTolerant 6T SRAM Using NMOS-Centered Cell Layout▼d・ S husuke YOSHIMOTO,S hunsukeO KUMURA, KojiN II,H iroshi KAWAGUCHI,and MAsahiko YOSHIMOTO
■300 ▼app. 1579
■7001 ▼a・ S husuke YOSHIMOTO,S hunsukeO KUMURA, KojiN II,H iroshi KAWAGUCHI,and MAsahiko YOSHIMOTO
■773 ▼tIEICE Transactions on Fundamentals of Electronics, Communications and ComputerSciences▼gv.E96-A n.7▼d2013, 07
■SIS ▼aKS027538▼b63145▼h1▼sG
