서브메뉴
검색
A 6 bit, 7 mW, 700MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation
A 6 bit, 7 mW, 700MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation
상세정보
- 자료유형
- 기사
- ISSN
- 09168508
- 서명/저자
- A 6 bit, 7 mW, 700MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation
- 형태사항
- pp. 422
- 모체레코드
- 모체정보확인
- Control Number
- gtec:383148
MARC
008171213s2013 aa eng■022 ▼a09168508
■245 ▼aA 6 bit, 7 mW, 700MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation
■300 ▼app. 422
■773 ▼tIEICE Transactions on Fundamentals of Electronics, Communications and ComputerSciences▼gv.E96-A n.2▼d2013, 02
■SIS ▼aKS027005▼b63145▼h1▼sG
