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Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder
Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder
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008171211s2010 aa eng■022 ▼a09168516
■245 ▼aConcurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder▼dLu, Y.-C.▼eLu, E.-H.
■300 ▼app. 1
■7001 ▼aLu, Y.-C.
■7001 ▼aLu, E.-H.
■773 ▼tIEICE Transactions on Communications▼gv.E93-B n.1▼d2010, 01
■SIS ▼aKS021655▼b63226▼h3▼sG
