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Formal Verification and Synthesis for Discrete-Time Stochastic Systems
Formal Verification and Synthesis for Discrete-Time Stochastic Systems
Detailed Information
- 자료유형
- 기사
- ISSN
- 00189286
- 서명/저자
- Formal Verification and Synthesis for Discrete-Time Stochastic Systems / Lahijanian, M. ; Andersson, S. B. ; Belta, C.
- 형태사항
- pp. 2031
- 기타저자
- Lahijanian, M.
- 기타저자
- Andersson, S. B.
- 기타저자
- Belta, C.
- 모체레코드
- 모체정보확인
- Control Number
- gtec:343228
MARC
008171010s2015 a a kor■022 ▼a00189286
■245 ▼aFormal Verification and Synthesis for Discrete-Time Stochastic Systems▼dLahijanian, M.▼eAndersson, S. B.▼eBelta, C.
■300 ▼app. 2031
■7001 ▼aLahijanian, M.
■7001 ▼aAndersson, S. B.
■7001 ▼aBelta, C.
■773 ▼tIEEE transactions on Automatic Control▼gv.60 n.8▼d2015, 08
■SIS ▼aKS031056▼b63263▼h3▼sG
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