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The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems
The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems / Hsu, P. ;...
The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems

Detailed Information

자료유형  
 기사
ISSN  
10518215
서명/저자  
The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems / Hsu, P. ; Shen, C.
형태사항  
pp. 1091
기타저자  
Hsu, P.
기타저자  
Shen, C.
기본자료저록  
IEEE transactions on circuits and systems for video technology : v.27 n.5 2017, 05
모체레코드  
모체정보확인
Control Number  
gtec:329833

MARC

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■245    ▼aThe  VLSI  Architecture  of  a  Highly  Efficient  Deblocking  Filter  for  HEVC  Systems▼dHsu,  P.▼eShen,  C.
■300    ▼app.  1091
■7001  ▼aHsu,  P.
■7001  ▼aShen,  C.
■773    ▼tIEEE  transactions  on  circuits  and  systems  for  video  technology▼gv.27  n.5▼d2017,  05
■SIS    ▼aKS034262▼b63262▼h3▼sG

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