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The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems
The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems
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008170919s2017 a a kor■022 ▼a10518215
■245 ▼aThe VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems▼dHsu, P.▼eShen, C.
■300 ▼app. 1091
■7001 ▼aHsu, P.
■7001 ▼aShen, C.
■773 ▼tIEEE transactions on circuits and systems for video technology▼gv.27 n.5▼d2017, 05
■SIS ▼aKS034262▼b63262▼h3▼sG
