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Algorithm and Architecture Design of the H.265/HEVC Intra Encoder
Algorithm and Architecture Design of the H.265/HEVC Intra Encoder
Detailed Information
- 자료유형
- 기사
- ISSN
- 10518215
- 서명/저자
- Algorithm and Architecture Design of the H.265/HEVC Intra Encoder / Pastuszak, G. ; Abramowski, A
- 형태사항
- pp. 210
- 기타저자
- Pastuszak, G.
- 기타저자
- Abramowski, A
- 모체레코드
- 모체정보확인
- Control Number
- gtec:329317
MARC
008170918s2016 a a kor■022 ▼a10518215
■245 ▼aAlgorithm and Architecture Design of the H.265/HEVC Intra Encoder▼dPastuszak, G.▼eAbramowski, A
■300 ▼app. 210
■7001 ▼aPastuszak, G.
■7001 ▼aAbramowski, A
■773 ▼tIEEE transactions on circuits and systems for video technology▼gv.26 n.1▼d2016, 01
■SIS ▼aKS031847▼b63262▼h3▼sG
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