서브메뉴
검색
Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering
Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering
상세정보
- 자료유형
- 기사
- ISSN
- 10518215
- 서명/저자
- Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering / Hautala, I. ; Boutellier, J. ; Hannuksela, J.
- 형태사항
- pp. 1217
- 기타저자
- Hautala, I.
- 기타저자
- Boutellier, J.
- 기타저자
- Hannuksela, J.
- 모체레코드
- 모체정보확인
- Control Number
- gtec:329238
MARC
008170918s2015 a a kor■022 ▼a10518215
■245 ▼aProgrammable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering▼dHautala, I.▼eBoutellier, J.▼eHannuksela, J.
■300 ▼app. 1217
■7001 ▼aHautala, I.
■7001 ▼aBoutellier, J.
■7001 ▼aHannuksela, J.
■773 ▼tIEEE transactions on circuits and systems for video technology▼gv.25 n.7▼d2015, 07
■SIS ▼aKS030940▼b63262▼h3▼sG
