서브메뉴
검색
Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems
Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems
Detailed Information
- 자료유형
- 기사
- ISSN
- 10518215
- 서명/저자
- Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems / He, K. ; Gerstlauer, A. ; Orshansky, M
- 형태사항
- pp. 961
- 기타저자
- He, K.
- 기타저자
- Gerstlauer, A.
- 기타저자
- Orshansky, M
- 모체레코드
- 모체정보확인
- Control Number
- gtec:329096
MARC
008170918s2013 a a kor■022 ▼a10518215
■245 ▼aCircuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems▼dHe, K.▼eGerstlauer, A.▼eOrshansky, M
■300 ▼app. 961
■7001 ▼aHe, K.
■7001 ▼aGerstlauer, A.
■7001 ▼aOrshansky, M
■773 ▼tIEEE transactions on circuits and systems for video technology▼gv.23 n.6▼d2013, 06
■SIS ▼aKS027553▼b63262▼h3▼sG
Preview
Export
ChatGPT Discussion
AI Recommended Related Books
ค้นหาข้อมูลรายละเอียด
- จองห้องพัก
- Book Loan Request Service
- โฟลเดอร์ของฉัน
