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Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing
Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing
상세정보
- 자료유형
- 기사
- ISSN
- 10518215
- 서명/저자
- Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing / Hubert, H. ; Stabernack, B. ; Zilly, F
- 형태사항
- pp. 813
- 기타저자
- Hubert, H.
- 기타저자
- Stabernack, B.
- 기타저자
- Zilly, F
- 모체레코드
- 모체정보확인
- Control Number
- gtec:329084
MARC
008170918s2013 a a kor■022 ▼a10518215
■245 ▼aArchitecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing▼dHubert, H.▼eStabernack, B.▼eZilly, F
■300 ▼app. 813
■7001 ▼aHubert, H.
■7001 ▼aStabernack, B.
■7001 ▼aZilly, F
■773 ▼tIEEE transactions on circuits and systems for video technology▼gv.23 n.5▼d2013, 05
■SIS ▼aKS027352▼b63262▼h3▼sG
