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Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform
Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform
Detailed Information
- 자료유형
- 기사
- ISSN
- 10518215
- 서명/저자
- Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform / Hsia, C. H. ; Chiang, J. S. ; Guo, J. M.
- 형태사항
- pp. 671
- 기타저자
- Hsia, C. H.
- 기타저자
- Chiang, J. S.
- 기타저자
- Guo, J. M.
- 모체레코드
- 모체정보확인
- Control Number
- gtec:329073
MARC
008170918s2013 a a kor■022 ▼a10518215
■245 ▼aMemory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform▼dHsia, C. H.▼eChiang, J. S.▼eGuo, J. M.
■300 ▼app. 671
■7001 ▼aHsia, C. H.
■7001 ▼aChiang, J. S.
■7001 ▼aGuo, J. M.
■773 ▼tIEEE transactions on circuits and systems for video technology▼gv.23 n.4▼d2013, 04
■SIS ▼aKS027252▼b63262▼h3▼sG
