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Development of Chip Shrink Technology for Lateral-Type GaN based HFETs Using SiO2/ Polyinide Dual IMD Layers
Development of Chip Shrink Technology for Lateral-Type GaN based HFETs Using SiO2/ Polyinide Dual IMD Layers
상세정보
- 자료유형
- 기사
- ISSN
- 17388090
- 서명/저자
- Development of Chip Shrink Technology for Lateral-Type GaN based HFETs Using SiO2/ Polyinide Dual IMD Layers / Seung kyu Oh ; Hwa-Young Ko
- 형태사항
- pp. 213
- 기타저자
- Seung kyu Oh
- 기타저자
- Hwa-Young Ko
- 모체레코드
- 모체정보확인
- Control Number
- gtec:290553
MARC
008150402s2015 a a eng■022 ▼a17388090
■245 ▼aDevelopment of Chip Shrink Technology for Lateral-Type GaN based HFETs Using SiO2/ Polyinide Dual IMD Layers▼dSeung kyu Oh▼eHwa-Young Ko
■300 ▼app. 213
■7001 ▼aSeung kyu Oh
■7001 ▼aHwa-Young Ko
■773 ▼tElectronic Materials Letters▼gv.11 n.2▼d2015, 03
■SIS ▼aKS030308▼b63247▼h3▼sG
