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Synthesis of arithmetic circuits : FPGA, ASIC and embedded systems
Synthesis of arithmetic circuits : FPGA, ASIC and embedded systems / Jean-Pierre Deschamp...
Synthesis of arithmetic circuits : FPGA, ASIC and embedded systems

Detailed Information

자료유형  
 단행본
ISBN  
0471687839
UDC  
681.3.021
DDC  
005.43 J43s-23
청구기호  
005.43 J43s
저자명  
Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter
서명/저자  
Synthesis of arithmetic circuits : FPGA, ASIC and embedded systems / Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter
발행사항  
Hoboken, N.J. : John Wiley & Sons, 2006
형태사항  
556p. : 삽도 ; 25cm
가격  
＄132.00
Control Number  
gtec:21977

MARC

 008080725s2006        us  a                    000      eng
■020    ▼a0471687839
■0801  ▼a681.3.021
■082    ▼a005.43▼bJ43s▼223
■090    ▼a005.43▼bJ43s
■1001  ▼aJean-Pierre  Deschamps,  Gery  Jean  Antoine  Bioul,  Gustavo  D.  Sutter
■24510▼aSynthesis  of  arithmetic  circuits▼b  FPGA,  ASIC  and  embedded  systems▼dJean-Pierre  Deschamps,  Gery  Jean  Antoine  Bioul,  Gustavo  D.  Sutter
■260    ▼aHoboken,  N.J.▼bJohn  Wiley  &  Sons▼c2006
■300    ▼a556p.▼b삽도▼c25cm
■9500  ▼b＄132.00

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