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Computer architecture: : a quantitatice approach/
Computer architecture: : a quantitatice approach/
Detailed Information
- 자료유형
- 단행본
- ISBN
- 1-55860-724-2
- UDC
- 681.3.02
- DDC
- 004.16 J65c-23
- 청구기호
- 004.16 J65c
- 서명/저자
- Computer architecture: a quantitatice approach/ John L. Hennessy, David A.Patterson
- 판사항
- 3rd ed
- 발행사항
- 미국: : Morgan Kaufmann Publishers,Inc,, 2003
- 형태사항
- 1v.(various pagings)p.: : 삽도; ; 25cm
- 주기사항
- Includes bibliographical references and index.
- 내용주기
- 완전내용Foreword부분내용vii완전내용Preface부분내용xvii완전내용Acknowledgments부분내용xxv완전내용Chapter 1 Fundamentals of Computer Design부분내용2완전내용Chapter 2 Instruction Set Principles and Examples부분내용90완전내용Chapter 3 Instruction-Level Parallelism and Its Dynamic Exploitation부분내용172완전내용Chapter 4 Exploiting Instruction-Level Parallelism with Software Approaches부분내용304완전내용Chapter 5 Memory Hierachy Design부분내용390완전내용Chapter 6 Multiprocessors and Thread-Level Parallelism부분내용528완전내용Chapter 7 Storage Systems부분내용67800완전내용Chapter 8 Interconnection Networks and Clusters부분내용78811완전내용Appendix A Pipelining: Basic and Intermediate Concepts22완전내용Appendix B Solutions to Selected Exercises33완전내용Appendix C A Survey of RISC Architectures for Desktop, Sever, and Embedded Computers44완전내용Appendix D An Alternative to RISC: The Intel 80x8655완전내용Appendix E Another Alternative to RISC: The VAX Architecture66완전내용Appendix F The IBM 360/370 Architecture for Mainframe Computers77완전내용Appendix G Vector Processors88완전내용Appendix H Computer Arithmetic99완전내용Appendix I Implementing Coherence Protocols00완전내용References부분내용R-111완전내용Index부분내용I-122
- 가격
- $89.95
- Control Number
- gtec:11787
MARC
008041221s2003 us a 000a eng■020 ▼a1-55860-724-2
■0801 ▼a681.3.02
■082 ▼a004.16▼bJ65c▼223
■090 ▼a004.16▼bJ65c
■1001 ▼aJohn L. Hennessy, David A. Patterson
■24510▼aComputer architecture:▼c a quantitatice approach/▼dJohn L. Hennessy, David A.Patterson
■250 ▼a3rd ed
■260 ▼a미국:▼bMorgan Kaufmann Publishers,Inc,▼c2003
■300 ▼a1v.(various pagings)p.:▼b삽도;▼c25cm
■500 ▼aIncludes bibliographical references and index.
■505 ▼aForeword▼cvii▼aPreface▼cxvii▼aAcknowledgments▼cxxv▼aChapter 1 Fundamentals of Computer Design▼c2▼aChapter 2 Instruction Set Principles and Examples▼c90▼aChapter 3 Instruction-Level Parallelism and Its Dynamic Exploitation▼c172▼aChapter 4 Exploiting Instruction-Level Parallelism with Software Approaches▼c304▼aChapter 5 Memory Hierachy Design▼c390▼aChapter 6 Multiprocessors and Thread-Level Parallelism▼c528▼aChapter 7 Storage Systems▼c67800▼aChapter 8 Interconnection Networks and Clusters▼c78811▼aAppendix A Pipelining: Basic and Intermediate Concepts22▼aAppendix B Solutions to Selected Exercises33▼aAppendix C A Survey of RISC Architectures for Desktop, Sever, and Embedded Computers44▼aAppendix D An Alternative to RISC: The Intel 80x8655▼aAppendix E Another Alternative to RISC: The VAX Architecture66▼aAppendix F The IBM 360/370 Architecture for Mainframe Computers77▼aAppendix G Vector Processors88▼aAppendix H Computer Arithmetic99▼aAppendix I Implementing Coherence Protocols00▼aReferences▼cR-111▼aIndex▼cI-122
■9500 ▼b$89.95
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