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Digital design from zero to one/
Digital design from zero to one/
Detailed Information
- 자료유형
- 단행본
- ISBN
- 0-471-12447-8
- UDC
- 621.38
- DDC
- 621.3815 D186d-23
- 청구기호
- 621.3815 D186d
- 서명/저자
- Digital design from zero to one/ Jerry D. Daniels
- 발행사항
- 미국: : John Wiley & Sons, Inc,, 1996
- 형태사항
- 616p.: : 삽도; ; 25cm
- 주기사항
- Includes bibliographical references and index.
- 내용주기
- 완전내용PREFACE부분내용v완전내용PART ONE COMBINATIONAL LOGIC부분내용1완전내용1. FROM NUMBERS TO SWITCHES부분내용3완전내용2. TRUTH TABLES AND BOOLEAN ALGEBRA부분내용78완전내용3. MAP AND TABLE METHODS FOR MINIMIZING BOOLEAN EXPRESSIONS부분내용154완전내용4. PROGRAMMABLE CIRCUITS FOR COMBINATIONAL DESIGN부분내용199완전내용PART TWO SEQUENTIAL DESIGN부분내용249완전내용5. EVOLUTION OF FLIP-FLOPS부분내용251완전내용6. sYNCHRONOUS COUNTERS부분내용303완전내용7. SYNCHRONOUS FINITE STATE MACHINES부분내용35700완전내용PART THREE MASTERING DESIGN부분내용42511완전내용8. MEMORY부분내용42722완전내용9. DIGITAL COMMUNICATION AND SERIAL TRANSMISSION부분내용48233완전내용10. ARITHMETIC HARDWARE부분내용52444완전내용11. REGISTER TRANSFER LOGIC부분내용57555완전내용INDEX부분내용61066
- 가격
- ＄125.00
- Control Number
- gtec:11785
MARC
008041221s1996 us a 000a eng■020 ▼a0-471-12447-8
■0801 ▼a621.38
■082 ▼a621.3815▼bD186d▼223
■090 ▼a621.3815▼bD186d
■1001 ▼aDaniels, Jerry D.
■24510▼aDigital design from zero to one/▼dJerry D. Daniels
■260 ▼a미국:▼bJohn Wiley & Sons, Inc,▼c1996
■300 ▼a616p.:▼b삽도;▼c25cm
■500 ▼aIncludes bibliographical references and index.
■505 ▼aPREFACE▼cv▼aPART ONE COMBINATIONAL LOGIC▼c1▼a1. FROM NUMBERS TO SWITCHES▼c3▼a2. TRUTH TABLES AND BOOLEAN ALGEBRA▼c78▼a3. MAP AND TABLE METHODS FOR MINIMIZING BOOLEAN EXPRESSIONS▼c154▼a4. PROGRAMMABLE CIRCUITS FOR COMBINATIONAL DESIGN▼c199▼aPART TWO SEQUENTIAL DESIGN▼c249▼a5. EVOLUTION OF FLIP-FLOPS▼c251▼a6. sYNCHRONOUS COUNTERS▼c303▼a7. SYNCHRONOUS FINITE STATE MACHINES▼c35700▼aPART THREE MASTERING DESIGN▼c42511▼a8. MEMORY▼c42722▼a9. DIGITAL COMMUNICATION AND SERIAL TRANSMISSION▼c48233▼a10. ARITHMETIC HARDWARE▼c52444▼a11. REGISTER TRANSFER LOGIC▼c57555▼aINDEX▼c61066
■9500 ▼b＄125.00
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